1. Field of the Invention
The present invention relates to the manufacturing of semiconductor devices. More particularly, the present invention relates to a method of forming a fine pattern of a semiconductor device using a double patterning technique, e.g., using two generally coplanar hard mask patterns.
2. Description of the Related Art
A highly integrated semiconductor device referred to as a nanoscale device is formed of patterns whose features have widths and pitches (critical dimensions) below the resolution limits of photolithography. One such pattern of a highly integrated semiconductor device is an isolation layer which is used to define active regions of the device. The isolation layer is formed by producing a trench/recess in a substrate and filling the trench/recess with an insulating material. However, it is difficult to fill the trench/recess adequately with insulating material when sections of the trench/recess are narrow and the pitch of the sections of the trench/recess is fine, i.e., it is difficult to form an isolation layer whose critical dimensions are on the order of nanometers.